Verilog Program for Implementation of Logic Function with test bench

If you are given a logic equqtion, use the code below and implement the function: Here is the program:
/* Verilog Program to implement the function f=x+y’z and Testbench for all the possible inputs using For Loop

Verilog code by Vivek.R
 visit me @ http://vivek.techiestuffs.com
 contact me @ vividvilla@gmail.com

*/

module imp_func_1(f,x,y,z);
 output f; // output variable
 input x,y,z; //Input variables
 assign f=(x|((~y)&z));
 endmodule

module imp_func_tb();
 wire f_tb;
 reg x_tb,y_tb,z_tb;
 integer i,j,k;
 imp_func_1 ex(f_tb,x_tb,y_tb,z_tb);

initial
 begin
 $display ("time,\t X,\t Y,\t Z,\t F");
 for(i=1'b0;i<=1'b1;i=i+1'b1)
 for(j=1'b0;j<=1'b1;j=j+1'b1)
 for(k=1'b0;k<=1'b1;k=k+1'b1)
 begin
 #10 x_tb=i;y_tb=j;z_tb=k;
 $monitor ("%g,\t %b,\t %b,\t %b,\t %b",$time,x_tb,y_tb,z_tb,f_tb);
 end
 end
 endmodule

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