Verilog Program for Complex Adder/Subtractor and Complex Multiplier with Test bench

Complex Numbers are denoted in the form ” a+ib “
where a is the real part and b is the imaginary part.
The basic rules of the complex numbers addition and multiplication are directly applicable here and can be used in the program.
COMLEX ADDER & SUBTRACTOR

/* Code writen by Anand.K
Contact me at itsexzion@gmail.com */

module complex(c1,c2,c3,c4);
input [15:0]c1,c2;
output [31:0]c3,c4;
assign c3={(c1[15:8]+c2[15:8]),(c1[7:0]+c2[7:0])}; //addition//
assign c4={(c1[15:8]-c2[15:8]),(c1[7:0]-c2[7:0])}; //subtraction//
endmodule

module complex_tb();
 reg [15:0]c1_tb,c2_tb;
 wire [15:0]c3_tb,c4_tb;
 complex a(c1_tb,c2_tb,c3_tb,c4_tb);
 initial
 begin
 c1_tb<=16'b0000100000001000;
 c2_tb<=16'b0000000000001000;
 #50
 $display("output for add %b",c3_tb);
 $display("output for add %b",c4_tb);
 end
endmodule

COMPLEX MULTIPLIER

/* Code writen by Anand.K
Contact me at itsexzion@gmail.com */

module compmul(c1,c2,product);
input [15:0]c1,c2;
output [31:0]product;
assign product={((c1[15:8]*c2[15:8])-(c1[7:0]*c2[7:0])),((c1[15:8]*c2[7:0])+(c1[7:0]*c2[15:8]))};
endmodule

module compmul_tb();
 reg [15:0]c1_tb,c2_tb;
 wire [31:0]product_tb;
 compmul a(c1_tb,c2_tb,product_tb);
 initial
 begin
 c1_tb<=16'b0000001000000010;
 c2_tb<=16'b0000011000000010;
 #50
 $display("output for mul %b",product_tb);
 end
endmodule

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