Metal-Semiconductor Junctions

Introduction

Metal-to-semiconductor (M-S) junctions are of great importance since they are present in every semiconductor device. They can behave either as a Schottky barrier or as an ohmic contact dependent on the characteristics of the interface. We will primarily focus on Schottky barriers. This chapter contains an analysis of the electrostatics of the M-S junction, including the calculated of the charge, field and potential distribution within the device. This chapter also contains a derivation of the current voltage characteristics due to diffusion, thermionic emission and tunneling in Metal-Semiconductor junctions, followed by a discussion of M-S contacts and MESFETs.

Structure

The structure of a metal-semiconductor junction is shown in Figure 3.2.1. It consists of a metal contacting a piece of semiconductor. An ideal Ohmic contact, a contact such that no potential exists between the metal and the semiconductor, is made to the other side of the semiconductor. The sign convention of the applied voltage and current is also shown on Figure 3.2.1.

Figure 3.2.1 :

Structure and sign convention of a metal-semiconductor junction

3.2.2. Flatband diagram and built-in potential

The barrier between the metal and the semiconductor can be identified on an energy band diagram. To construct such diagram we first consider the energy band diagram of the metal and the semiconductor, and align them using the same vacuum level as shown in Figure 3.2.2 (a). As the metal and semiconductor are brought together, the Fermi energies of the metal and the semiconductor do not change right away. This yields the flatband diagram of Figure 3.2.2 (b).

Figure 3.2.2 :

Energy band diagram of the metal and the semiconductor before (a) and after (b) contact is made.

The barrier height, fB, is defined as the potential difference between the Fermi energy of the metal and the band edge where the majority carriers reside. From Figure 3.2.2 (b) one finds that for an n-type semiconductor the barrier height is obtained from:

(3.2.1)

Where FM is the work function of the metal and c is the electron affinity. The work function of selected metals as measured in vacuum can be found in Table 3.2.1. For p-type material, the barrier height is given by the difference between the valence band edge and the Fermi energy in the metal:

(3.2.2)

A metal-semiconductor junction will therefore form a barrier for electrons and holes if the Fermi energy of the metal as drawn on the flatband diagram is somewhere between the conduction and valence band edge.

In addition, we define the built-in potential, fI, as the difference between the Fermi energy of the metal and that of the semiconductor.

(3.2.3)

(3.2.4)

The measured barrier height for selected metal-semiconductor junctions is listed in Table 3.2.1. These experimental barrier heights often differ from the ones calculated using (3.2.1) or (3.2.2). This is due to the detailed behavior of the metal-semiconductor interface. The ideal metal-semiconductor theory assumes that both materials are infinitely pure, that there is no interaction between the two materials and no unwanted interfacial layer. Chemical reactions between the metal and the semiconductor alter the barrier height as do interface states at the surface of the semiconductor and interfacial layers. Some general trends however can still be observed. As predicted by (3.2.1),the barrier height on n-type semiconductors increases for metals with a higher work function as can be verified for silicon. Gallium arsenide on the other hand is known to have a large density of surface states so that the barrier height becomes virtually independent of the metal. Furthermore, one finds that the barrier heights reported in the literature to vary widely due to different surface cleaning procedures.

Table 3.2.1:

Workfunction in units of eV of selected metals and their measured barrier height on germanium, silicon and gallium arsenide.

Example 3.1	Consider a chrome-silicon metal-semiconductor junction with Nd = 1017 cm-3. Calculate the barrier height and the built-in potential. Repeat for a p-type semiconductor with the same doping density.
Solution	The barrier height equals: Note that this value differs from the one listed in Table 3.2.1 since the work function in vacuum was used. See the discussion in the text for more details. The built-in potential equals (using (3.2.3) and (2.6.12)): The barrier height for the chrome/p-silicon junction equals: And the built-in potential equals:

3.2.3. Thermal equilibrium

The flatband diagram, shown in Figure 3.2.2 (b), is not a thermal equilibrium diagram, since the Fermi energy in the metal differs from that in the semiconductor. Electrons in the n-type semiconductor can lower their energy by traversing the junction. As the electrons leave the semiconductor, a positive charge, due to the ionized donor atoms, stays behind. This charge creates a negative field and lowers the band edges of the semiconductor. Electrons flow into the metal until equilibrium is reached between the diffusion of electrons from the semiconductor into the metal and the drift of electrons caused by the field created by the ionized impurity atoms. This equilibrium is characterized by a constant Fermi energy throughout the structure.

Figure 3.2.3 :

Energy band diagram of a metal-semiconductor contact in thermal equilibrium.

It is of interest to note that in thermal equilibrium, i.e. with no external voltage applied, there is a region in the semiconductor close to the junction ( ???? ), which is depleted of mobile carriers. We call this the depletion region. The potential across the semiconductor equals the built-in potential, fi.

3.2.4. Forward and reverse bias

Operation of a metal-semiconductor junction under forward and reverse bias is illustrated with Figure 3.2.4. As a positive bias is applied to the metal (Figure 3.2.4 (a)), the Fermi energy of the metal is lowered with respect to the Fermi energy in the semiconductor. This results in a smaller potential drop across the semiconductor. The balance between diffusion and drift is disturbed and more electrons will diffuse towards the metal than the number drifting into the semiconductor. This leads to a positive current through the junction at a voltage comparable to the built-in potential.

Figure 3.2.4 :

Energy band diagram of a metal-semiconductor junction under (a) forward and (b) reverse bias

As a negative voltage is applied (Figure 3.2.4 (b)),the Fermi energy of the metal is raised with respect to the Fermi energy in the semiconductor. The potential across the semiconductor now increases, yielding a larger depletion region and a larger electric field at the interface. The barrier, which restricts the electrons to the metal, is unchanged so that that barrier, independent of the applied voltage, limits the flow of electrons. The metal-semiconductor junction with positive barrier height has therefore a pronounced rectifying behavior. A large current exists under forward bias, while almost no current exists under reverse bias.

The potential across the semiconductor therefore equals the built-in potential, fi, minus the applied voltage, Va.

(3.2.5)

Electrostatic analysis General discussion - Poisson's equation The electrostatic analysis of a metal-semiconductor junction is of interest since it provides knowledge about the charge and field in the depletion region. It is also required to obtain the capacitance-voltage characteristics of the diode. The general analysis starts by setting up Poisson's equation: (3.3.1) Where the charge density, r, is written as a function of the electron density, the hole density and the donor and acceptor densities. To solve the equation, we have to express the electron and hole density, n and p, as a function of the potential, f, yielding: (3.3.2) with (3.3.3) where the potential is chosen to be zero in the n-type region, where x >> xn. This second-order non-linear differential equation (3.3.2) cannot be solved analytically. Instead we will make the simplifying assumption that the depletion region is fully depleted and that the adjacent neutral regions contain no charge. This full depletion approximation is the topic of section 3.3.2. 3.3.2 Full depletion approximation The simple analytic model of the metal-semiconductor junction is based on the full depletion approximation. This approximation is obtained by assuming that the semiconductor is fully depleted over a distance xd, called the depletion region. While this assumption does not provide an accurate charge distribution, it does provide very reasonable approximate expressions for the electric field and potential throughout the semiconductor. These are derived in section 3.3.3. 3.3.3 Full depletion analysis We now apply the full depletion approximation to an M-S junction containing an n-type semiconductor. We define the depletion region to be between the metal-semiconductor interface (x = 0) and the edge of the depletion region (x = xd). The depletion layer width, xd, is unknown at this point but will later be expressed as a function of the applied voltage. To find the depletion layer width, we start with the charge density in the semiconductor and calculate the electric field and the potential across the semiconductor as a function of the depletion layer width. We then solve for the depletion layer width by requiring the potential across the semiconductor to equal the difference between the built-in potential and the applied voltage, fi - Va. The different steps of the analysis are illustrated by Figure 3.3.1. As the semiconductor is depleted of mobile carriers within the depletion region, the charge density in that region is due to the ionized donors. Outside the depletion region, the semiconductor is assumed neutral. This yields the following expressions for the charge density, r: (3.3.4) where we assumed full ionization so that the ionized donor density equals the donor density, Nd. This charge density is shown in Figure 3.3.1 (a). The charge in the semiconductor is exactly balanced by the charge in the metal, QM, so that no electric field exists except around the metal-semiconductor interface. Figure 3.3.1 : (a) Charge density, (b) electric field, (c) potential and (d) energy as obtained with the full depletion analysis. Using Gauss's law we obtain the electric field as a function of position, also shown in Figure 3.3.1 (b): (3.3.5) where es is the dielectric constant of the semiconductor. We also assumed that the electric field is zero outside the depletion region, since a non-zero field would cause the mobile carriers to redistribute until there is no field. The depletion region does not contain mobile carriers so that there can be an electric field. The largest (absolute) value of the electric field is obtained at the interface and is given by: (3.3.6) where the electric field was also related to the total charge (per unit area), Qd, in the depletion layer. Since the electric field is minus the gradient of the potential, one obtains the potential by integrating the expression for the electric field, yielding: (3.3.7) We now assume that the potential across the metal can be neglected. Since the density of free carriers is very high in a metal, the thickness of the charge layer in the metal is very thin. Therefore, the potential across the metal is several orders of magnitude smaller than that across the semiconductor, even though the total amount of charge is the same in both regions. The total potential difference across the semiconductor equals the built-in potential, fi,in thermal equilibrium and is further reduced/increased by the applied voltage when a positive/negative voltage is applied to the metal as described by equation (3.2.5). This boundary condition provides the following relation between the semiconductor potential at the surface, the applied voltage and the depletion layer width: (3.3.8) Solving this expression for the depletion layer width, xd, yields: (3.3.9) 3.3.4. Junction capacitance In addition, we can obtain the capacitance as a function of the applied voltage by taking the derivative of the charge with respect to the applied voltage yielding: (3.3.10) The last term in the equation indicates that the expression of a parallel plate capacitor still applies. This can be explained by the fact that the charge added/removed from the depletion layer as one decreases/increases the applied voltage is added/removed only at the edge of the depletion region. While the parallel plate capacitor expression seems to imply that the capacitance is constant, the metal-semiconductor junction capacitance is not constant since the depletion layer width, xd, varies with the applied voltage. Example 3.2 Consider a chrome-silicon metal-semiconductor junction with Nd = 1017 cm-3. Calculate the depletion layer width, the electric field in the silicon at the metal-semiconductor interface, the potential across the semiconductor and the capacitance per unit area for an applied voltage of -5 V. Solution The depletion layer width equals: where the built-in potential was already calculated in Example 3.1. The electric field in the semiconductor at the interface is: The potential equals: And the capacitance per unit area is obtained from: 3.3.5. Schottky barrier lowering Image charges build up in the metal electrode of a metal-semiconductor junction as carriers approach the metal-semiconductor interface. The potential associated with these charges reduces the effective barrier height. This barrier reduction tends to be rather small compared to the barrier height itself. Nevertheless this barrier reduction is of interest since it depends on the applied voltage and leads to a voltage dependence of the reverse bias current. Note that this barrier lowering is only experienced by a carrier while approaching the interface and will therefore not be noticeable in a capacitance-voltage measurement. An energy band diagram of an n-type silicon Schottky barrier including the barrier lowering is shown in Figure 3.3.2: Figure 3.3.2: Energy band diagram of a silicon Schottky barrier with fB = 0.8 V and Nd = 1019 cm-3. Shown is the energy band diagram obtained using the full-depletion approximation, the potential reduction experienced by electrons, which approach the interface and the resulting conduction band edge. A rounding of the conduction band edge can be observed at the metal-semiconductor interface as well as a reduction of the height of the barrier. The calculation of the barrier reduction assumes that the charge of an electron close to the metal-semiconductor interface attracts an opposite surface charge, which exactly balances the electron's charge so that the electric field surrounding the electron does not penetrate beyond this surface charge. The time to build-up the surface charge and the time to polarize the semiconductor around the moving electron are assumed to be much shorter than the transit time of the electron . This scenario is based on the assumption that there are no mobile or fixed charges around the electron as it approaches the metal-semiconductor interface. The electron and the induced surface charges are shown in Figure 3.3.3: Figure 3.3.3: a) Field lines and surface charges due to an electron in close proximity to a perfect conductor and b) the field lines and image charge of an electron. It can be shown that the electric field in the semiconductor is identical to that of the carrier itself and another carrier with opposite charge at equal distance but on the opposite side of the interface. This charge is called the image charge. The difference between the actual surface charges and the image charge is that the fields in the metal are distinctly different. The image charge concept is justified on the basis that the electric field lines are perpendicular to the surface a perfect conductor, so that, in the case of a flat interface, the mirror image of the field lines provides continuous field lines across the interface. The barrier lowering depends on the square root of the electric field at the interface and is calculated from: (3.3.11) 3.3.6. Derivation of Schottky barrier lowering We now derive equation (3.3.11) by calculating the potential due to the image charge and adding it to the potential within the depletion region. The electrostatic force between the two particles, one with a positive electronic charge and the other with a negative electronic charge, which are both a distance, x, away from the interface (x = 0), is given by: (3.3.12) The corresponding potential equals: (3.3.13) which combined with the potential variation due to the electric field yields the following potential energy, V(x), versus position, x: (3.3.14) where the field due to the charge in the depletion region is assumed to be constant and set equal to the maximum field, Emax: (3.3.15) At this point the question arises why a single electron can noticeably alter the potential, while the depletion layer contains significantly more charge. To understand this, one has to realize that we have assumed that the charge in the depletion region is not quantized, but instead is distributed throughout the depletion layer. While this assumption does provide the correct average potential it does not accurately reflect the potential variations due to the individual charges of the ionized donors or mobile electrons. As we assumed that the single electron is far away from all other charges in the semiconductor, the potential energy due to all those charges is close to the average potential energy. The potential energy due to the distributed charge of the ionized donors and a single electron reaches its maximum value at: (3.3.16) and the corresponding maximum value of the potential energy equals: (3.3.17) where DfB is the barrier height reduction given by: (3.3.18) 3.3.7. Solution to Poisson’s Equation To assess the error made when using the full depletion approximation we now derive the correct solution by solving Poisson's equation analytically. The actual solution for the potential is then obtained by numerically integrating the expression for the electric field. We start from the charge density, r, in a semiconductor for the general case where electrons, holes, ionized acceptors and ionized donors are present: (3.3.19) where f is the potential in the semiconductor. The potential is chosen to equal zero deep into the semiconductor. For an n-type semiconductor without acceptors or free holes this can be further reduced to: (3.3.20) assuming the semiconductor to be non-degenerate and fully ionized. A similar expression can be obtained for p-type material. Poisson's law can then be rewritten as: (3.3.21) Multiplying both sides with df/dx, this equation can be integrated between an arbitrary point x and infinity. The electric field at infinity (deep in the semiconductor) is taken to be zero. The electric field for a given potential is then: (3.3.22) Where the sign function equals +1 or -1 depending on the sign of f and LD is the Debye length given by, ??????? . Equation (3.3.22) is plotted in Figure 3.3.4 using normalized parameters. Depletion occurs for negative potentials while accumulation occurs for positive potentials. Figure 3.3.4: Absolute value of the normalized electric field, |E| LD/Vt, versus normalized potential, f/Vt Applying Gauss's law (Q = esE), we then find the relation between the total charge in the semiconductor region and the total potential across the semiconductor. The capacitance can also be obtained from: (3.3.23) where fs is the potential across the semiconductor and equals -fI + Va. This expression can be approximated for fs< 0 and |fs| >> Vt , yielding: (3.3.24) This expression equals (3.3.10) as derived using the full depletion approximation, except for the added term, Vt, in the denominator. This expression yields the capacitance value with a relative accuracy better than 0.3 % for Va < fi – 6Vt. 3.3.7.1 Numeric solution Numeric solution A numeric solution can be obtained by integrating equation (3.3.21). The solution to the energy band diagram, the charge density, the electric field and the potential are shown in the figures below: Integration was started four Debye lengths to the right of the edge of the depletion region as obtained using the full depletion approximation. Initial conditions were obtained by assuming the potential at the starting point to be adequately expressed by a solution to the homogenous equation: (3.3.25) Shown are solutions for a gold-silicon M-S junction with FM = 4.75V, c = 4.05V, Nd = 1016 cm-3 and es/e0 = 11.9. Figure 3.3.5: Energy band diagram of an M-S junction Figure 3.3.6: Charge density versus position in a M-S junction. The solid line is the numeric solution, and the dotted line is the solution based on the full depletion approximation. Figure 3.3.7: Electric field versus distance in a M-S junction. The solid line is the numeric solution, and the dotted line is the solution based on the full depletion approximation. Figure 3.3.8: Potential versus distance of an M-S junction. The solid line is the numeric solution, and the dotted line is the solution based on the full depletion approximation. Schottky diode current The current across a metal-semiconductor junction is mainly due to majority carriers. Three distinctly different mechanisms exist: diffusion of carriers from the semiconductor into the metal, thermionic emission of carriers across the Schottky barrier and quantum-mechanical tunneling through the barrier. The diffusion theory assumes that the driving force is distributed over the length of the depletion layer. The thermionic emission theory on the other hand postulates that only energetic carriers, those, which have an energy equal to or larger than the conduction band energy at the metal-semiconductor interface, contribute to the current flow. Quantum-mechanical tunneling through the barrier takes into account the wave-nature of the electrons, allowing them to penetrate through thin barriers. In a given junction, a combination of all three mechanisms could exist. However, typically one finds that only one current mechanism dominates. The analysis reveals that the diffusion and thermionic emission currents can be written in the following form: (3.4.1) This expression states that the current is the product of the electronic charge, q, a velocity, v, and the density of available carriers in the semiconductor located next to the interface. The velocity equals the mobility multiplied with the field at the interface for the diffusion current and the Richardson velocity (see section 3.4.2) for the thermionic emission current. The minus one term ensures that the current is zero if no voltage is applied as in thermal equilibrium any motion of carriers is balanced by a motion of carriers in the opposite direction. The tunneling current is of a similar form, namely: (3.4.2) where vR is the Richardson velocity and n is the density of carriers in the semiconductor. The tunneling probability term, Q, is added since the total current depends on the carrier flux arriving at the tunnel barrier multiplied with the probability, Q, that they tunnel through the barrier. 3.4.1. Diffusion current This analysis assumes that the depletion layer is large compared to the mean free path, so that the concepts of drift and diffusion are valid. The resulting current density equals: (3.4.3) The current therefore depends exponentially on the applied voltage, Va, and the barrier height, fB. The prefactor can more easily be understood if one rewrites it as a function of the electric field at the metal-semiconductor interface, max: (3.4.4) yielding: (3.4.5) so that the prefactor equals the drift current at the metal-semiconductor interface, which for zero applied voltage exactly balances the diffusion current. 3.4.2 Thermionic emission The thermionic emission theory assumes that electrons, with an energy larger than the top of the barrier, will cross the barrier provided they move towards the barrier. The actual shape of the barrier is hereby ignored. The current can be expressed as: (3.4.6) where is the Richardson constant and fB is the Schottky barrier height. The expression for the current due to thermionic emission can also be written as a function of the average velocity with which the electrons at the interface approach the barrier. This velocity is referred to as the Richardson velocity given by: (3.4.7) So that the current density becomes: (3.4.8) 3.4.3. Tunneling The tunneling current is obtained from the product of the carrier charge, velocity and density. The velocity equals the Richardson velocity, the velocity with which on average the carriers approach the barrier. The carrier density equals the density of available electrons, n, multiplied with the tunneling probability, Q, yielding: (3.4.9) Where the tunneling probability is obtained from: (3.4.10) and the electric field equals = fB/L. The tunneling current therefore depends exponentially on the barrier height, fB, to the 3/2 power. 3.4.4. Derivation of the Metal-Semiconductor Junction Current 3.4.4.1 Derivation of the diffusion current 3.4.4.2 Derivation of the thermionic emission current 3.4.4.3 Derivation of the tunneling current 3.4.4.1 Derivation of the diffusion current We start from the expression for the total current and then integrate it over the width of the depletion region: (3.4.11) which can be rewritten by using = -df/dx and multiplying both sides of the equation with exp(-f/Vt), yielding: (3.4.12) Integration of both sides of the equation over the depletion region yields: (3.4.13) Where the values listed in Table 3.4.1 were used for the electron density and the potential: Table 3.4.1: Boundary conditions used to solve equation (3.4.13) and f* = f + fI - Va. The integral in the denominator can be solved using the potential obtained from the full depletion approximation solution, or: (3.4.14) so that f* can be written as: (3.4.15) where the second term is dropped since the linear term is dominant if x << xsub>d. Using this approximation one can solve the integral as: (3.4.16) for (fi – Va) > Vt. This yields the final expression for the current due to diffusion: (3.4.17) This expression indicates that the current depends exponentially on the applied voltage, Va, and the barrier height, fB. The prefactor can be understood physically if one rewrites that term as a function of the electric field at the metal-semiconductor interface, max: (3.4.18) yielding: (3.4.19) so that the prefactor equals the drift current at the metal-semiconductor interface, which for zero applied voltage exactly balances the diffusion current. 3.4.4.2 Derivation of the thermionic emission current The thermionic emission theory assumes that electrons, which have an energy larger than the top of the barrier will cross the barrier, provided they move towards the barrier. The actual shape of the barrier is hereby ignored. The current can be expressed as: (3.4.20) For non-degenerately doped material, the density of electrons between E and E + dE is given by: (using (2.4.7) and assuming EF,n < Ec - 3kT) (3.4.21) Assuming a parabolic conduction band (with constant effective mass m*), the carrier energy, E, can be related to its velocity, v, by: (3.4.22) Combining (3.4.21) with (3.4.22) yields: (3.4.23) when replacing v2 by vx2 + vy2 +vz2 and 4p v2dv by dvxdvydvz the current becomes: (3.4.24) using (3.4.25) The velocity vox is obtained by setting the kinetic energy equal to the potential across the n-type region: (3.4.26) so that vox is the minimal velocity of an electron in the quasi-neutral n-type region, needed to cross the barrier. Using (3.4.27) which is valid for a metal-semiconductor junction, one obtains: (3.4.28) where is the Richardson constant and fB is the Schottky barrier height which equals the difference between the Fermi level in the metal, EF,M and the conduction band edge, Ec, evaluated at the interface between the metal and the semiconductor. The -1 term is added to account for the current flowing from right to left. The current flow from right to left is independent of the applied voltage since the barrier is independent of the band bending in the semiconductor and equal to fB. Therefore it can be evaluated at any voltage. For Va = 0 the total current must be zero, yielding the -1 term. The expression for the current due to thermionic emission can also be written as a function of the average velocity with which the electrons at the interface approach the barrier. This velocity is referred to as the Richardson velocity given by: (3.4.29) So that the current density becomes: (3.4.30) 3.4.4.3 Derivation of the tunneling current To derive the tunnel current, we start from the time independent Schrödinger equation: (3.4.31) which can be rewritten as (3.4.32) Assuming that V(x) - E is independent of position in a section between x and x+dx this equation can be solved yielding: (3.4.33) The minus sign is chosen since we assume that the particle moves from left to right. For a slowly varying potential the amplitude of the wave function at x = L can be related to the wave function at x = 0 : (3.4.34) This equation is referred to as the WKB approximation. From this the tunneling probability, Q, can be calculated for a triangular barrier for which V(x)-E = qfB (1- x/L) (3.4.35) The tunneling probability then becomes: (3.4.36) where the electric field equals = fB/L. The tunneling current is obtained from the product of the carrier charge, velocity and density. The velocity equals the Richardson velocity, the velocity with which on average the carriers approach the barrier while the carrier density equals the density of available electrons multiplied with the tunneling probability, yielding: (3.4.37) The tunneling current therefore depends exponentially on the barrier height to the 3/2 power . Metal-Semiconductor Contacts   Metal-semiconductor contacts are an obvious component of any semiconductor device. At the same time, such contacts cannot be assumed to have a resistance as low as that of two connected metals. In particular, a large mismatch between the Fermi energy of the metal and semiconductor can result is a high-resistance rectifying contact. A proper choice of materials can provide a low resistance Ohmic contact. However for a lot of semiconductors there is no appropriate metal available. Instead one then creates a tunnel contact. Such contact consists of a thin barrier – obtained by heavily-doping the semiconductor – through which carriers can readily tunnel. Thin interfacial layers also affect contact formation. Most metal-semiconductor contacts are annealed or alloyed after the initial deposition of the metal in an effort to further improve the contact resistivity. This section describes each of these contacts as well as an analysis of the contact resistance between a metal and a thin semiconductor layer. 3.5.1. Ohmic contacts A metal-semiconductor junction results in an Ohmic contact (i.e. a contact with voltage independent resistance) if the Schottky barrier height, fB, is zero or negative. In such case, the carriers are free to flow in or out of the semiconductor so that there is a minimal resistance across the contact. For an n-type semiconductor, this means that the workfunction of the metal must be close to or smaller than the electron affinity of the semiconductor. For a p-type semiconductor, it requires that the workfunction of the metal must be close to or larger than the sum of the electron affinity and the bandgap energy. Since the workfunction of most metals is less than 5 V and a typical electron affinity is about 4 V, it can be problematic to find a metal that provides an Ohmic contact to p-type semiconductors with a large bandgap such as GaN or SiC. 3.5.2. Tunnel contacts An alternate and more practical contact is a tunnel contact. Such contacts do have a positive barrier at the metal-semiconductor interface, but also have a high enough doping in the semiconductor that there is only a thin barrier separating the metal from the semiconductor. If the width of the depletion region at the metal-semiconductor interface is very thin, on the order of 3 nm or less, carriers can readily tunnel across such barrier. The required doping density for such contact is 1019 cm-3 or higher. 3.5.3. Annealed and alloyed contacts The fabrication of Ohmic contacts frequently includes a high temperature step so that the deposited metals can either alloy with the semiconductor or the high-temperature anneal reduces the unintentional barrier at the interface. In the case of silicon, one can simply deposit a metal such as aluminum and obtain a reasonable Ohmic contact. However, subsequent annealing at 475°C in a reducing ambient such as forming gas (20:1 N2/H2) will further improve the contact resistivity. The temperature is chosen below the eutectic temperature of the Si/Al eutectic composition. Annealing at higher temperature causes the formation of Si/Al alloys, which in turn causes pits in the silicon. This effect is also referred to as spiking and when penetrating through an underlying p-n junction these “spikes” dramatically affect the quality of the p-n junction as can be observed in the form of an enhanced leakage current or reduced breakdown voltage. The use of a reducing atmosphere avoids any further oxidation of the metal during annealing, while it can also reduce any interfacial oxide between the metal and semiconductor. Aluminum deposited onto low-doped silicon (< 1015 cm-3) tends to form Schottky barriers, so that it is advantageous to provided a more-highly doped contact region underneath the contact metal. The small barrier height can be overcome through thermionic emission, while the contact resistance is further improved by creating a tunnel barrier using degenerately doped contact layers. Contacts to compound semiconductors require some more attention. Selecting a material with the right workfunction might still not result in the expected Ohmic contact. This is caused by pinning of the Fermi energy at the interface due to the large number of surface states at the metal-semiconductor interface. This only leaves the tunnel contact as a viable low resistance contact. To further improve the tunnel contact one adds dopants such as germanium in the case of an n-type contact and zinc in the case of a p-type contact to the metal. An anneal at 400°C in a forming gas ambient for ten minutes causes the dopants to alloy with the semiconductor, thereby forming a thin high-doped region as desired for a tunnel contact. 3.5.4. Contact resistance to a thin semiconductor layer The contact between a metal and a thin semiconductor layer can be described with the resistive network shown in Figure 3.5.1. This equivalent circuit is obtained by slicing the structure into small sections with length Dx, so that the contact resistance, R1, and the semiconductor resistance, R2, are given by: (3.5.1) and (3.5.2) where rc is the contact resistance of the metal-to-semiconductor interface per unit area with units of Wcm2, Rs is the sheet resistance of the semiconductor layer with units of W/o Ohms per square), and W is the width of the contact. Figure 3.5.1 : Distributed resistance model of a contact to a thin semiconductor layer. Using Kirchoff's laws one obtains the following relations between the voltage, V(x), across the M-S interface and the current, I(x), parallel to the interface at x and x + Dx. (3.5.3) (3.5.4) By letting Dx approach zero one finds the following differential equations for the current, I(x), and voltage, V(x): (3.5.5) (3.5.6) These equations can be combined into: (3.5.7) The parameter l is the characteristic distance over which the current changes under the metal contact and is also referred to as the penetration length. The general solution for I(x) and V(x) are: (3.5.8) (3.5.9) Both are plotted in Figure 3.5.2: Figure 3.5.2: Lateral current and voltage underneath a 5 mm long and 1 mm wide metal contact with a contact resistivity of 10-5 W-cm2 on a thin semiconductor layer with a sheet resistance of 100 W/o. The total resistance of the contact is: (3.5.10) In the limit for an infinitely long contact (or d >> l) the contact resistance is given by: (3.5.11) A measurement of the resistance between a set of contacts with a variable distance L between the contacts (also referred to as a TLM structure) can therefore be fitted to the following straight line: (3.5.12) so that the resistance per square, Rs, can be obtained from the slope, while the contact resistivity, rc, can be obtained from the intersection with the y-axis. The penetration depth, l, can be obtained from the intersection with the x-axis. This is illustrated with Figure 3.5.3. Figure 3.5.3: Resistance versus contact spacing, L, of a TLM structure. In the limit for a short contact (or d << l), the contact resistance can be approximated by expanding the hyperbolic cotangent: (3.5.13) The total resistance of a short contact therefore equals the resistance between the contact metal and the semiconductor layer (i.e. the parallel connection of all the resistors, R1, in Figure 3.5.1), plus one third of the end-to-end resistance of the conducting layer underneath the contact metal (i.e. the series connection of all resistors, R2, in Figure 3.5.1). Metal-Semiconductor Field Effect Transistor (MESFETs) The Metal-Semiconductor-Field-Effect-Transistor (MESFET) consists of a conducting channel positioned between a source and drain contact region as shown in the Figure 3.6.1. The carrier flow from source to drain is controlled by a Schottky metal gate. The control of the channel is obtained by varying the depletion layer width underneath the metal contact which modulates the thickness of the conducting channel and thereby the current between source and drain. Figure 3.6.1 : Structure of a MESFET with gate length, L, and channel thickness, d. The key advantage of the MESFET is the higher mobility of the carriers in the channel as compared to the MOSFET. Since the carriers located in the inversion layer of a MOSFET have a wavefunction, which extends into the oxide, their mobility - also referred to as surface mobility - is less than half of the mobility of bulk material. As the depletion region separates the carriers from the surface their mobility is close to that of bulk material. The higher mobility leads to a higher current, transconductance and transit frequency of the device. The disadvantage of the MESFET structure is the presence of the Schottky metal gate. It limits the forward bias voltage on the gate to the turn-on voltage of the Schottky diode. This turn-on voltage is typically 0.7 V for GaAs Schottky diodes. The threshold voltage therefore must be lower than this turn-on voltage. As a result it is more difficult to fabricate circuits containing a large number of enhancement-mode MESFET. The higher transit frequency of the MESFET makes it particularly of interest for microwave circuits. While the advantage of the MESFET provides a superior microwave amplifier or circuit, the limitation by the diode turn-on is easily tolerated. Typically depletion-mode devices are used since they provide a larger current and larger transconductance and the circuits contain only a few transistors, so that threshold control is not a limiting factor. The buried channel also yields a better noise performance as trapping and release of carriers into and from surface states and defects is eliminated. The use of GaAs rather than silicon MESFETs provides two more significant advantages: first, the electron mobility at room temperature is more than 5 times larger, while the peak electron velocity is about twice that of silicon. Second, it is possible to fabricate semi-insulating (SI) GaAs substrates, which eliminates the problem of absorbing microwave power in the substrate due to free carrier absorption. The threshold voltage, VT, of a MESFET is the voltage required to fully deplete the doped channel layer. This threshold voltage equals: (3.6.1) where fi is the built-in potential and d is the thickness of the doped region. This threshold voltage can also be written as a function of the pinch-off voltage VP: (3.6.2) Where the pinch-off voltage equals: (3.6.3) The derivation of the current in a MESFET starts by considering a small section of the device between y and y + dy. The current density at that point can be written as a function of the gradient of the channel voltage: (3.6.4) The drain current is related to the current density and the part of the MESFET channel that is not depleted. (3.6.5) Where the depletion layer width at position y is related to the channel voltage, VC(y), by: (3.6.6) The equation for the current can now be integrated from source to drain, yielding: (3.6.7) Since the steady-state current in the device is independent of position, the left hand term equals ID times L so that: (3.6.8) Integration results in: (3.6.9) This result is valid as long as the width of the un-depleted channel (d – xn(y)) is positive, namely for: (3.6.10) This condition also defines the quadratic region of a MESFET. For larger drain voltage, the current saturates and equals that at (3.6.11) The corresponding current is the saturation current, ID,sat: (3.6.12) An example of the resulting I-V characteristics is shown in Figure 3.6.2. The corresponding device parameters are listed in Table 3.6.1 Figure 3.6.2: Drain current versus Drain-Source voltage at a gate-source voltage of 0.2, 0.4, 0.6 0.8 and 1.0 Volt for a silicon MESFET with built-in potential of 1 V. Channel parameters and device dimensions are listed in Table 3.6.1. The transfer characteristic of a MESFET is shown in Figure 3.6.3 and compared to a quadratic expression of the form: (3.6.13) where is the average depletion layer width in the channel layer. The quadratic expression yields the same current at VG = fi for = 3d/8. The close fit is at times used to justify using the simpler quadratic equation. Figure 3.6.3: Transfer characteristic of a MESFET. Shown is the square root of the drain current of the MESFET (solid line) and a quadratic fit with =3d/8 (dotted line). Schottky diode with an interfacial layer A more elaborate model of the Schottky barrier contains an interfacial layer between the semiconductor and the metal. Typically this layer is a thin oxide layer, with thickness d, which naturally forms on the surface of a semiconductor when exposed to air. The analysis of the Schottky diode can now be repeated using the full depletion approximation yielding the following relation between the total applied voltage and the depletion layer width: (3.7.1) from which the depletion layer width can be solved. The capacitance of the structure can be obtained from the series connection of the oxide and semiconductor capacitance: (3.7.2) with (3.7.3) This expression is very similar to that of equation (3.3.10) except that the oxide layer increases the built-in voltage. The potential fn across the semiconductor can be written as: (3.7.4) Or alternatively, (3.7.5) for zero applied voltage this reduces to: (3.7.6) instead of simply fn = fi when no oxide is present. This analysis can be interpreted as follows: the interfacial layer reduces the capacitance of the Schottky barrier diode, although a capacitance measurement will have the same general characteristics as an ideal Schottky barrier diode except that the built-in voltage is increased. However the potential across the semiconductor is decreased due to the voltage drop across the oxide layer, so that at low voltage the barrier for electrons flowing into the semiconductor is reduced yielding a higher current that without the oxide. This analysis assumes that the interfacial layer forms a very thin tunnel barrier, which at low voltages does not restrict the current. As the voltage applied to the Schottky barrier is more positive, the depletion layer width reduces, so that the field in the oxide also reduces and with it the voltage drop across the oxide. The current under forward bias conditions therefore approaches that of the ideal Schottky diode until the tunnel barrier restricts the current flow. This results in a higher ideality factor for Schottky barrier with an interfacial layer. From equations (3.7.3) and (3.7.4) we find that the effect is largest for highly doped semiconductors and interfacial layers with low dielectric constant. The current under forward bias is then given by: (3.7.7) or: (3.7.8) which, around a specific value of Va , can be written as: (3.7.9) with ideality, n: (3.7.10) and saturation current Is*: (3.7.11) At Va = 0 the saturation current becomes: (3.7.12) As a result, an interfacial layer between the metal and semiconductor of a Schottky diode affects both the measured barrier height and built-in potential. The total potential within the device is now divided between the interfacial layer and the semiconductor. This causes the potential across the semiconductor to be lower so that carriers can more easily flow from the semiconductor into the metal, yielding a larger current. The interfacial layer also reduces the capacitance. As an example we consider a thin 3 nm thick oxide layer at the interface of a gold-silicon Schottky diode. The energy band diagram is shown in Figure 3.7.1. Figure 3.7.1: Energy band diagram of a gold-silicon M-S junction with a 3 nm interfacial oxide layer. (Va = 0.3 V and Nd = 1018 cm-3) Since the interfacial layer can be viewed as an additional capacitor connected in series with the capacitance associated with the depletion layer, the total capacitance is lower than for a diode without an interfacial layer. A 1/C2 plot versus the applied voltage is shown in Figure 3.7.2. Figure 3.7.2: Capacitance-Voltage characteristics of a gold-silicon M-S junction with (solid line) and without (dashed line) a 3 nm interfacial oxide layer. (Nd = 1018 cm-3) This plot reveals that the slope remains the same, while the intercept with the voltage axis shifts to higher forward voltages. The slope remains unchanged since it depends on the doping concentration in the semiconductor, which remains unchanged. The presence of an interfacial layer therefore increases the measured built-in potential, but does not alter the extracted doping concentration. The analysis of the forward bias current is more complex since it depends on the transport properties of the interfacial layer. However, if one assumes that the barrier is so thin that carriers can easily tunnel through, the diode current analysis can be obtained from the standard diffusion analysis, provided that the altered potential across the semiconductor is taken into account. A comparison of the current through a gold-silicon junction with and without an interfacial layer is shown in Figure 3.7.3. The figure reveals that the interfacial layer affects both the slope and the intercept of the forward-biased current-voltage when plotted on a semi-logarithmic scale. Figure 3.7.3: Current-Voltage characteristics of a gold-silicon M-S junction with (solid line) and without (dashed line) a 3 nm interfacial oxide layer. (Is = 10-10 A and Nd = 1018 cm-3) In summary, an interfacial layer increases the built-in potential as measured with a C-V measurement, decreases the internal potential across the semiconductor, which increases the measured ideality factor and saturation current. It also decreases the measured barrier height as extracted from the temperature dependence of the saturation current and limits the maximum current density. Other Unipolar Junctions The metal-semiconductor junction is the most studied unipolar junction, be not the only one that occurs in semiconductor devices. Two other unipolar junctions are the n-n+ homojunction and the n-n+ Heterojunction. The n-n+ homojunction frequently occurs in semiconductor devices are heavily doped regions are commonly added to reduce the overall resistance and improve the contact resistivity. Most textbooks ignore the effect of such junctions as the analysis is more difficult and the overall effect on the device is typically small. We present the electrostatic analysis of the n-n+ here in part for completeness but also to set the stage for the analysis of the n-n+ heterojunction. The n-n+ heterojunction frequently occurs in heterojunction devices. Such occurrence is not always deliberate, but their analysis is , albeit complex, need when optimizing a Heterojunction device design. In this section we present the electrostatic analysis of the n-n+ homojunction and heterojunction as well as the analysis of the n-n+ heterojunction current. 3.8.1. The n-n+ homojunction When contacting semiconductor devices one very often includes highly doped semiconductor layers to lower the contact resistance between the semiconductor and the metal contact. This added layer causes a n-n+ junction within the device. Most often these junctions are ignored in the analysis of devices, in part because of the difficulty treating them correctly, in part because they can simply be ignored. The build-in voltage of a n-n+ junction is given by: (3.8.1) Which means that the built-in voltage is about 59.4 meV if the doping concentrations differ by a factor 10. It is because of this small built-in voltage that this junction is often ignored. However large variations in doping concentration do cause significant potential variations. The influence of the n-n+ junction must be evaluated in conjunction with its current voltage characteristics: if the n-n+ junction is in series with a p-n diode, the issue is whether or not the n-n+ junction affects the operation of the p-n junction in any way. At low current densities one can expect the p-n diode to dominate the current flow, whereas at high current densities the n-n+ junction could play a role if not designed properly. For the analysis of the n-n+ junction we start from a flat band energy band diagram connecting the two regions in absence of an electric field. One can visualize that electrons will flow from the n+ region and accumulate in the n-type region. However, since the carrier concentration must be continuous (this is only required in a homojunction), the carrier density in the n-type region is smaller that the doping concentration of the n+ region, and the n+ region is not completely depleted. The full depletion approximation is therefore not applicable. Instead one recognizes the situation to be similar to that of a metal-semiconductor junction: the n+ region is depleted but has a small voltage across the semiconductor as in a Schottky barrier with small applied voltage, whereas the n-type region is accumulated as in an Ohmic contact. A general solution of this structure requires the use of equation (3.3.2). An approximate solution can be obtained in the limit where the potential across both regions is smaller than the thermal voltage. The charge in the n-n+ structure region is then given by solving the linearized Poisson equation: (3.8.2) (3.8.3) where the n-n+ interface is located at x = 0, and LD,n and LD,n+ are the extrinsic Debye lengths in the material, given by: (3.8.4) (3.8.5) Applying Poisson's equation again one finds the potentials to be: (3.8.6) (3.8.7) The solutions for the charge density, electric field, potential and energy band diagram are plotted in the Figure 3.8.1: Figure 3.8.1 : Charge, electric field, potential and energy banddiagram in a silicon n-n+ structure with Nd = 1016 cm-3, Nd+ = 1017 cm-3 and Va = 0. 3.8.2 The n-n+ heterojunction 3.8.2.1 Analysis without quantization 3.8.2.2 Analysis including quantization 3.8.2.3 Comparison of the two solutions with and without quantization Heterojunctions can be found in a wide range of heterojunction devices including laser diodes, high electron mobility transistors (HEMTs) and heterojunction bipolar transistors (HBTs). Of those, the HEMT naturally contains such heterojunction, while the other devices could contain an unintentional n-n+ heterojunction. As a starting point of the analysis, consider a n-n+ heterojunction including a spacer layer with thickness d as shown in Figure 3.8.2. Figure 3.8.2: Flatband energy diagram of a n-n+ heterojunction including a spacer layer with thickness d. The built-in voltage for a n-n+ heterojunction with doping concentrations Nd and Nd+ is given by: (3.8.8) Where Nc,n and Nc,n+ are the effective densities of states of the low and high-doped region respectively. Unlike a homojunction, the heterojunction can have a built-in voltage, which is substantially larger than the thermal voltage. This justifies using the full depletion approximation for the depleted region. For the accumulated region one also has to consider the influence of quantization of energy levels as carriers are confined by the electric field and the hetero-interface. In the next two sections we analyze the energy band diagram of the n-n+ heterojunction with and without the inclusion of quantization and compare the two solutions. 3.8.2.1 Analysis without quantization For the classic case where the material does not become degenerate at the interface one can use (3.3.22) to find the total charge in the accumulation layer: (3.8.9) while the potentials and the field can be solved for a given applied voltage using: (3.8.10) (3.8.11) (3.8.12) The subscript sp refers to the undoped spacer layer with thickness d, which is located between the two doped regions. These equations can be solved by starting with a certain value of fn, which enables the calculation of the electric field, the other potentials and the corresponding voltage, Va. 3.8.2.2 Analysis including quantization The analysis of an n-n+ heterojunction including quantized levels is more complicated because the energy levels depend on the potential, which can only be calculated if the energy levels are known. A self-consistent calculation is therefore required to obtain a correct solution. An approximate method, which also clarifies the steps needed for a correct solution is described below. Starting from a certain density of electrons per unit area, Ns, which are present in the accumulation layer, one finds the field at the interface: (3.8.13) We assume that only the n = 1 energy level is populated with electrons. The minimal energy can be expressed as a function of the electric field: (3.8.14) The bandgap discontinuity DEc can then be related to the other potentials of the junction, yielding: (3.8.15) where the potentials, fn+ and fsp, in turn can be expressed as a function of n: (3.8.16) (3.8.17) These equations can be combined into one transcendental equation as a function of the electric field, n. (3.8.18) Once n is known all potentials can be obtained. 3.8.2.3 Comparison of the two solutions with and without quantization We now compare both approaches by presenting a numerical solution obtained by implementing the equations above for the case with as well as that without quantization. Keep in mind that neither is exact as it would require a self-consistent numerical analysis that includes the calculation of the potential based on the quantum mechanical distribution of the charge in each of the quantized levels. The energy band diagram and the sheet charge versus applied voltage are presented in Figure 3.8.3 and Figure 3.8.4 respectively. Figure 3.8.3: Energy banddiagram of a Al0.4Ga0.6As/GaAs n+-n heterostructure with Nd+ = 1017 cm-3, Nd = 1016 cm-3, d = 10 nm and Va = 0.15 V. Comparison of analysis without quantization (upper curve) to that with quantization (lower curve) Figure 3.8.4: Electron density, Ns, in the accumulation region versus applied voltage, Va, with quantization (top curve) and without quantization (bottom curve). From the figures one finds that the analysis without quantization predicts a larger barrier to the left of the interface and a larger sheet charge for a given voltage. The actual solution is expected to be somewhere in between the two presented here, especially for the case where more than one quantized level exists and is occupied. 3.8.3 Currents across a n+-n heterojunction 3.8.3.1 Thermionic emission current across a n+-n heterojunction 3.8.3.2 Calculation of the Current and quasi-Fermi level throughout a Depletion Region 3.8.3.3 Calculation of the current due to thermionic emission and drift/diffusion Current transport across a n+-n heterojunction is similar to that of a metal-semiconductor junction: Diffusion, thermionic emission as well as tunneling of carriers across the barrier can occur. However to identify the current components one must first identify the potentials fn+ and fn by solving the electrostatic problem. From the band diagram one finds that a barrier exists for electrons going from the n+ to the n-doped region as well as for electrons going in the opposite direction. The analysis in the first section discusses the thermionic emission and yields a closed form expression based on a set of specific assumptions. The derivation also illustrates how a more general expression could be obtained. The next section describes the current-voltage characteristics of carriers traversing a depletion region, while the last section discusses how both effects can be combined. 3.8.3.1 Thermionic emission current across a n+-n heterojunction The total current due to thermionic emission across the barrier is given by the difference of the current flowing from left to right and the current flowing from right to left. Rather than re-deriving the expression for thermionic emission, we will apply equation (3.4.6) to the n+-n heterojunction. One complication arises from the fact that the effective mass of the carriers is different on each side of the hetero-junction which would seem to indicate that the Richardson constant is different for carrier flow from left to right compared to the flow from right to left. A more detailed analysis reveals that the difference in effective mass causes a quantum mechanical reflection at the interface, causing carriers with the higher effective mass to be reflected back while carriers with the smaller effective mass are to first order unaffected. We therefore use equation (3.4.6) for flow in both directions while using the Richardson constant corresponding to the smaller of the two effective masses, yielding: (3.8.19) where the potentials are related to the applied voltage by: (3.8.20) and the built-in voltage is given by: (3.8.21) Combining these relations yields: (3.8.22) where the barrier height fB* is defined as: (3.8.23) Assuming full depletion in the n+ depletion region and using equation (3.8.9) for the accumulated region, the charge balance between the depletion and accumulation layer takes the following form: (3.8.24) Combining equations (3.2.20) with (3.2.16) yields a solution for fn+ and fn. For the special case where sn+Nd+ = snI>Nd and fn >>Vt these equations reduce to: (3.8.25) The current (given by (3.2.18)) can then be expressed as a function of the applied voltage Va (3.8.26) Whereas this expression is similar to that of a metal-semiconductor barrier, it differs in that the temperature dependence is somewhat modified and the reverse bias current increases almost linearly with voltage. Under reverse bias, the junction can be characterized as a constant resistance, RHJ, which equals: (3.8.27) where A is the area of the junction. This shows that the resistance changes exponentially with the barrier height. Grading of the heterojunction is typically used to reduce the spike in the energy band diagram and with it the resistance across the interface. 3.8.3.2 Calculation of the Current and quasi-Fermi level throughout a Depletion Region We typically assume the quasi-Fermi level to be constant throughout the depletion region. This assumption can be justified for a homojunction but is not necessarily correct for a heterojunction p-n diode. For a homojunction p-n diode we derived the following expression for the minority carrier density in the quasi-neutral region of a "long" diode (3.8.28) so that the maximum change in the quasi-Fermi level, which occurs at the edge of the depletion region, equals: (3.8.29) so that the change of the quasi-Fermi level can be ignored if the depletion region width is smaller than the diffusion length as is typically the case in silicon p-n diodes. For a hetero-junction p-n diode one can not assume that the quasi-Fermi level is continuous, especially when the minority carriers enter a narrow bandgap region in which the recombination rate is so high that the current is limited by the drift/diffusion current in the depletion region located in the wide bandgap semiconductor. The current density can be calculated from: (3.8.30) Assuming the field to be constant throughout the depletion region one finds for a constant current density the following expression for the carrier density at the interface: (3.8.31) While for zero current one finds, for an arbitrary field (3.8.32) Combining the two expressions we postulate the following expression for the carrier density: (3.8.33) The carrier density can also be expressed as a function of the total change in the quasi-Fermi level across the depletion region, DEfn; (3.8.34) which yields the following expressions for the current density due to drift/diffusion: (3.8.35) where is max the field at the heterojunction interface. If DEfn equals the applied voltage, as is the case for an n+-n heterostructure, this expression equals: (3.8.36) which reduces for a M-S junction to: (3.8.37) so that thermionic emission dominates for vR << mn max or when the drift velocity is larger than the Richardson velocity. 3.8.3.3 Calculation of the current due to thermionic emission and drift/diffusion The calculation of the current through an n+-n junction due to thermionic emission and drift/diffusion becomes straightforward once one realizes that the total applied voltage equals the sum of the quasi-Fermi level variation, DEfn, across each region. For this analysis we therefore rewrite the current expressions as a function of DEfn, while applying the expression for the drift/diffusion current to the n+ material. (3.8.38)            Currents through insulators Current mechanisms through materials, which do not contain free carriers, can be distinctly different from those in doped semiconductors or metals. The following section discusses Fowler-Nordheim Tunneling, Poole-Frenkel emission, Space charge effects as well as Ballistic transport. While these current mechanisms are not related to Metal-Semiconductor junctions, they are presented here since they represent unipolar current mechanisms. 3.9.1 Fowler-Nordheim tunneling Fowler-Nordheim tunneling has been studied extensively in Metal-Oxide-Semiconductor structures where it has been shown to be the dominant current mechanism, especially for thick oxides. The basic idea is that quantum mechanical tunneling from the adjacent conductor into the insulator limits the current through the structure. Once the carriers have tunneled into the insulator they are free to move within the valence or conduction band of the insulator. The calculation of the current is based on the WKB approximation (as derived section 3.3.4) yielding the following relation between the current density, JFN, and the electric field in the oxide, ox: (3.9.1) where fB is the barrier height at the conductor/insulator interface. To check for this current mechanism, experimental I-V characteristics are typically plotted as ln(JFN/ox2) versus 1/ox, a so-called Fowler-Nordheim plot. Provided the effective mass of the insulator is known (for SiO2, mox* = 0.42 m0) one can then fit the experimental data to a straight line yielding a value for the barrier height. It is this type of measurement, which has yielded experimental values for the conduction band difference between different metals and silicon dioxide. It is important to note that carriers must tunnel through the insulator, which requires: (3.9.2) as is typically the case for thick oxides and high electric fields. 3.9.2 Poole-Frenkel emission The expression for Fowler-Nordheim tunneling implies that carriers are free to move through the insulator. Whereas this is indeed the case in thermally grown silicon dioxide it is frequently not so in deposited insulators, which contain a high density of structural defects. Silicon nitride (Si3N4) is an example of such material. The structural defects cause additional energy states close to the band edge, called traps. These traps restrict the current flow because of a capture and emission process, thereby becoming the dominant current mechanism. The current is a simple drift current described by (3.9.3) while the carrier density depends exponentially on the depth of the trap, which is corrected for the electric field (3.9.4) The total current then equals: (3.9.5) The existence of a large density of shallow traps in CVD silicon nitride makes Poole-Frenkel emission a frequently observed and well-characterized mechanism. 3.9.3 Space charge limited current Both Fowler-Nordheim tunneling and Poole-Frenkel emission mechanism yield very low current densities with correspondingly low carrier densities. For structures where carriers can readily enter the insulator and freely flow through the insulator one finds that the resulting current and carrier densities are much higher. The high density of these charged carriers causes a field gradient, which limits the current density. This situation occurs in lowly doped semiconductors and vacuum tubes. We start from an expression for the drift current and Gauss's law (where we assume that the insulator contains no free carriers if no current flows) (3.9.6) (3.9.7) Positively charged holes are assumed in this derivation, but the result equally holds for electrons. Next we can eliminate the carrier density, p, yielding: (3.9.8) Integrating this expression from 0 to x, while we assuming the electric field to be zero at x = 0 one obtains: (3.9.9) integrating once again from x = 0 to x = d with V(0) = V and V(d) = 0, one finds: (3.9.10) from which one obtains the expression for the space-charge-limited current: (3.9.11) 3.9.4 Ballistic Transport in insulators Ballistic transport is carrier transport without scattering or any other mechanism, which would cause a loss of energy. Combining energy conservation, current continuity and Gauss's law one finds the following current-voltage relation: (3.9.12) where d is the thickness of the insulator and m* is the effective mass of the carriers.